A clock divider is a digital circuit used to create a slow "daughter" clock from a faster "parent" clock. It is a very useful and very simply circuit.
The most basic clock divider is a simple toggling flip flop, which divides the clock frequency in half. That is to say, the daughter clock produced by this divider has half the frequency of the parent clock. In this circuit, the output of a D flip-flop is inverted and fed back to the data input for the same flip-flop. The parent clock is used as the clock for the flip-flop, and the data output of the flip-flop (which was inverted and sent to the input) is used as the daughter clock. By nature of the flip-flop, the output will change on every rising edge of the input clock. Because of the inverted feedback, the flip-flop will toggle every clock cycle, which means that one the first rising edge, for instance, the output will be high for one clock cycle, on the next rising edge (of the input clock, that is), it will go low, and stay low for one cycle. This will go back and forth, and so the output is a square wave with twice the period of the input clock. In other words, half the frequency.
To construct a clock divider in general, we use a simple binary counter. To divide a frequency by a power of two, create a binary plus-1 up-counter (or down-counter, just not up-down), clocked by the parent clock. The daughter clock can be derived from the most significant bit of the counter. The rule is that the frequency of the daughter clock is equal to the frequency of the parent clock divided by two-raised-to-the-power of the number of bits in the counter. So if you have n bits in the counter clocked at frequency f, the daughter clock frequency will be 
. Note that the toggling flip-flop we had above can be seen as a one-bit counter. We therefore have n = 1, so the output frequency is 
, as we already established.
Now this is if you take the daughter clock as the most significant bit. Actually, you can take it from any of the bits, and then you just use i+1 in place of n, where i is the index of the bit you use, with the least significant bit being 0, the nest least significant is 1, and so on up to the most significant is n-1. You can of course use multiple bits to derive multiple clocks at different frequencies.
You aren't limited to powers of two for clock division, although those are certainly the easiest. To divide a frequency by any positive even integer value, use the circuit shown at right. We start with a binary counter like the one we used before. This counter needs to count up to at least half of what you want to divide the frequency by. It can count beyond, that's ok, because we are using a binary digital comparator to know when it reaches half of our target value. When this happens, the comparator will output a one, which will reset the counter to start over at 0, and will also provide the rising edge to toggle the D flip-flop at the end of the circuit. Note that, as with our divide-by-two circuit, the flip-flop only toggles when this happens, it doesn't somehow go through an entire cycle. So The output of our comparator has to go high twice to give us a full cycle of our output clock. That's why the other input to our comparator is half of what you want to divide the clock by.
So for example, if you want to divide a clock frequency by 14, the counter-limit would be 14/2, which is 7. Therefore, you can use a counter as small as 3 bits. A sample waveform for this circuit is shown below. At each of the four vertical cursors, the counter is being reset to 0. There is actually a very small time right before this where the output actually goes to 7, but since the clear and the comparator are asynchronous, as soon as that happens, the comparator outputs a 1 and clears the counter. You probably won't see this in a behavioral simulation, but it might be a problem if you're looking for really precise clock division in a real circuit. In this case, you probably just want to use a flip-flop or something to make the output of the comparator synchronized to the parent clock. This will change the timing a bit, and you'll probably want to invert the clock to that synchronizing flip-flop, but you can work that out on your own.
